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PD - 95425A
AUTOMOTIVE MOSFET
IRFR4104PBF IRFU4104PbF
HEXFET(R) Power MOSFET
D
Features
l l l l l l
Advanced Process Technology Ultra Low On-Resistance 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free
VDSS = 40V
G S
RDS(on) = 5.5m ID = 42A
Description
Specifically designed for Automotive applications, this HEXFET(R) Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.
D-Pak IRFR4104
I-Pak IRFU4104
Absolute Maximum Ratings
Parameter
ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Silicon Limited) ID @ TC = 100C Continuous Drain Current, VGS @ 10V ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current IDM
Max.
119 84 42 480 140 0.95 20
Units
A
PD @TC = 25C Power Dissipation Linear Derating Factor VGS Gate-to-Source Voltage EAS (Thermally limited) Single Pulse Avalanche Energyd Single Pulse Avalanche Energy Tested Value EAS (Tested ) IAR EAR TJ TSTG Avalanche CurrentA Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw
W W/C V mJ A mJ
h
145 310 See Fig.12a, 12b, 15, 16 -55 to + 175
g
C 300 (1.6mm from case ) 10 lbfyin (1.1Nym)
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount) Junction-to-Ambient
Typ.
Max.
1.05 40 110
Units
C/W
i
--- --- ---
HEXFET(R) is a registered trademark of International Rectifier.
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1
12/06/04
IRFR/U4104PbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. Typ. Max. Units
40 --- --- 2.0 58 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.032 4.3 --- --- --- --- --- --- 59 19 24 17 69 37 36 4.5 7.5 2950 660 370 2130 590 850 --- --- 5.5 4.0 --- 20 250 200 -200 89 --- --- --- --- --- --- --- nH --- --- --- --- --- --- --- pF ns nC nA V
Conditions
VGS = 0V, ID = 250A
V/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 42A
e
V S A
VDS = VGS, ID = 250A VDS = 10V, ID = 42A VDS = 40V, VGS = 0V VDS = 40V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V ID = 42A VDS = 32V VGS = 10V VDD = 20V ID = 42A RG = 6.8 VGS = 10V
e e
Between lead, 6mm (0.25in.) from package and center of die contact VGS = 0V VDS = 25V = 1.0MHz VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 32V, = 1.0MHz VGS = 0V, VDS = 0V to 32V
f
Source-Drain Ratings and Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- 28 24 42 A 480 1.3 42 36 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 42A, VGS = 0V TJ = 25C, IF = 42A, VDD = 20V di/dt = 100A/s
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFR/U4104PbF
1000
TOP 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V
VGS
1000
TOP
VGS
15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V
100
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
4.5V
10
10
4.5V 60s PULSE WIDTH Tj = 25C
1 0.1 0
60s PULSE WIDTH Tj = 175C
1 0.1 0
1
10
100 100
1
10
100 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
120
Gfs, Forward Transconductance (S)
T J = 25C
ID, Drain-to-Source Current ()
100 80 60
T J = 175C
T J = 175C
100
TJ = 25C 40 20 0 0 20 40 60 80 100 ID, Drain-to-Source Current (A)
10
VDS = 20V 60s PULSE WIDTH
1 4 6 8 10
VDS = 10V 380s PULSE WIDTH
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance Vs. Drain Current
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IRFR/U4104PbF
5000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
20 ID= 42A
VGS, Gate-to-Source Voltage (V)
4000
16
VDS= 32V VDS= 20V
C, Capacitance (pF)
3000
Ciss
12
2000
8
Coss
1000
4
Crss
0 1 10 100
0 0 20 40 60 80 100 QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000.0
10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
ISD, Reverse Drain Current (A)
ID, Drain-to-Source Current (A)
1000
100.0
T J = 175C
100 100sec 10 1msec 1 Tc = 25C Tj = 175C Single Pulse 0 1 10 10msec
10.0 T J = 25C 1.0 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-toDrain Voltage (V)
0.1 100 1000 VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFR/U4104PbF
RDS(on) , Drain-to-Source On Resistance (Normalized)
120 LIMITED BY PACKAGE 100
ID , Drain Current (A)
2.0
ID = 42A VGS = 10V
80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
1.5
1.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
T J , Junction Temperature (C)
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Normalized On-Resistance Vs. Temperature
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE )
0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1
J J 1 1 R1 R1 2 R2 R2 C 2
0.1
Ri (C/W) 0.5067 0.5428
i (sec) 0.000414 0.004081
0.01
Ci= i/Ri Ci= i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFR/U4104PbF
EAS, Single Pulse Avalanche Energy (mJ)
15V
600
500
VDS
L
DRIVER
ID 9.2A 13A BOTTOM 42A
TOP
400
RG
20V VGS
D.U.T
IAS tp
+ V - DD
A
300
0.01
200
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
100
0 25 50 75 100 125 150 175
Starting T J, Junction Temperature (C)
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS VG QGD
VGS(th) Gate threshold Voltage (V)
4.0
3.0
Charge
ID = 250A
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
2.0
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
T J , Temperature ( C )
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 14. Threshold Voltage Vs. Temperature
6
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IRFR/U4104PbF
1000
Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax
Avalanche Current (A)
100
0.01 0.05
10
0.10
1
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
160
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 42A
120
80
40
0 25 50 75 100 125 150
Starting T J , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. 175 D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 16. Maximum Avalanche Energy Vs. Temperature
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IRFR/U4104PbF
Driver Gate Drive
D.U.T
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
RD
V DS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
D.U.T.
+
-VDD
Fig 18a. Switching Time Test Circuit
VDS 90%
10% VGS
td(on) tr t d(off) tf
Fig 18b. Switching Time Waveforms
8
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IRFR/U4104PbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120 WITH ASS EMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN T HE ASS EMBLY LINE "A" Note: "P" in as sembly line pos ition indicates "Lead-F ree" PART NUMBER INTERNATIONAL RECT IFIER LOGO
IRFU120 12 916A 34
ASS EMBLY LOT CODE
DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A
OR
PART NUMBER INT ERNAT IONAL RECT IF IER LOGO
IRFU120 12 34
DATE CODE P = DESIGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 16 A = AS SEMBLY S ITE CODE
AS SEMBLY LOT CODE
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IRFR/U4104PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120 WIT H ASS EMBLY LOT CODE 5678 ASS EMBLED ON WW 19, 1999 IN T HE AS SEMB LY LINE "A" Note: "P" in ass embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO PART NUMBER
IRFU120 919A 56 78
AS SEMBLY LOT CODE
DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A
OR
INTERNATIONAL RECTIFIER LOGO PART NUMBER
IRFU120 56 78
AS S EMBLY LOT CODE
DAT E CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = ASS EMBLY SITE CODE
10
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IRFR/U4104PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25C, L = 0.16mH Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive RG = 25, IAS = 42A, VGS =10V. Part not avalanche performance. recommended for use above this value. This value determined from sample failure population. 100% Pulse width 1.0ms; duty cycle 2%. tested to this value in production. When mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994 Repetitive rating; pulse width limited by Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site.
Notes:
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04
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11
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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